Bibliographic Database

Found 8 results
Filters: Author is Mamatha, I.  [Clear All Filters]
2018
Nair, M., I.. Mamatha, and S.. Tripathi, "Distributed Arithmetic based Hybrid Architecture for Multiple Transforms", International Conference signal Processing and Communication (ICSC 2018): Springer, 2018.
2017
Mamatha, I.., S.. Tripathi, and TSB.. Sudarshan, "Convolution Based Efficient Architecture for 1-D DWT", Computing, Communication and Automation, International Conference on: IEEE, 2017.
2016
Mamatha, I.., S.. Tripathi, and TSB.. Sudarshan, "Pipelined Architecture for Filter Bank Based 1-D DWT", Signal Processing and Integrated Networks (SPIN), 2016 3rd International Conference on: IEEE, pp. 47-52, 2016.
2015
Sai, SVB. Bala., I.. Mamatha, S.. Tripathi, and TSB.. Sudarshan, "Modified MLBF Based Architecture for 1-D DWT", Computational Intelligence and Computing Research (ICCIC), 2015 IEEE International Conference on: IEEE, pp. 1-4, 2015.
Mamatha, I.., N.. J Raj, S.. Tripathi, and TSB.. Sudarshan, "Systolic Architecture Implementation of 1D DFT and 1D DCT", Signal Processing, Informatics, Communication and Energy Systems (SPICES), 2015 IEEE International Conference on: IEEE, pp. 1-5, 2015.
Mamatha, I.., TSB.. Sudarshan, S.. Tripathi, and N.. Bhattar, "Triple Matrix Product Based 2D Systolic Implementation of Discrete Fourier Transform", Circuits, Systems, and Signal Processing, vol. 34, issue 10: Springer US, pp. 3221-3239, 2015.
2014
Mamatha, I.., TSB.. Sudarshan, S.. Tripathi, and N.. Bhattar, "Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product", Advances in Signal Processing and Intelligent Recognition Systems: Springer, Cham, pp. 311-322, 2014.
2013
Mamatha, I.., N.. J Raj, S.. Tripathi, and TSB.. Sudarshan, "Reduced Complexity Architecture for Convolution Based Discrete Cosine Transform", Electronic System Design (ISED), 2013 International Symposium on: IEEE, pp. 67-71, 2013.