Bibliographic Database

Found 7 results
Filters: Author is Mamatha, I  [Clear All Filters]
2016
Chandran, V., I. Mamatha, and S.. Tripathi, "NEDA based hybrid architecture for DCTΓÇöHWT", International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA): IEEE, pp. 1-6, 2016.
Mamatha, I., S.. Tripathi, and TSB. Sudarshan, "Pipelined architecture for filter bank based 1-D DWT", 3rd International Conference on Signal Processing and Integrated Networks (SPIN): IEEE, pp. 47-52, 2016.
2015
SaiBala, SVB., I. Mamatha, S.. Tripathi, and TSB. Sudarshan, "Modified MLBF based architecture for 1-D DWT", IEEE International Conference on Computational Intelligence and Computing Research (ICCIC): IEEE, pp. 1-4, 2015.
Mamatha, I., RJ. Nikhita, S.. Tripathi, and TSB. Sudarshan, "Systolic architecture implementation of 1D DFT and 1D DCT", Signal Processing, Informatics, Communication and Energy Systems (SPICES), 2015 IEEE International Conference on: IEEE, pp. 1-5, 2015.
Mamatha, I., TSB. Sudarshan, S.. Tripathi, and N. Bhattar, "Triple-Matrix Product-Based 2D Systolic Implementation of Discrete Fourier Transform", Circuits, Systems, and Signal Processing, vol. 34, issue 10: Springer US, pp. 3221-3239, 2015.
2014
Mamatha, I., S.. Tripathi, TSB. Sudarshan, and N. Bhattar, "Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product", Advances in Signal Processing and Intelligent Recognition Systems: Springer, Cham, pp. 311-322, 2014.
2013
Mamatha, I., RJ. Nikhita, S.. Tripathi, and TSB. Sudarshan, "Reduced complexity architecture for convolution based discrete cosine transform", International Symposium on Electronic System Design (ISED): IEEE, pp. 67-71, 2013.