Bibliographic Database

Found 4 results
Filters: Author is Ganesh, TS.  [Clear All Filters]
Ganesh, TS.., M. T. Frederick, TSB.. Sudarshan, and A. K. Somani, "Hashchip: A shared-resource multi-hash function processor architecture on FPGA", Integration, the VLSI Journal, Elsevier, vol. 40, issue 1: Elsevier, pp. 11-19, 2007.
Ganesh, TS.., and TSB.. Sudarshan, "ASIC Implementation of a Unified Hardware Architecture for Non-Key Based Cryptographic Hash Primitives", Information Technology: Coding and Computing, 2005. ITCC 2005. International Conference on, vol. 1: IEEE, pp. 580-585, 2005.
Sudarshan, TSB.., and TS.. Ganesh, "Hardware Architectures for Message Padding in Cryptograhic Hash Primitives", Proceedings of 8th IEEE Workshop on Progress in VLSI Design & Test (VDAT), pp. 136-144, 2004.
Ganesh, TS.., TSB.. Sudarshan, N. Kumar. Srinivasan, and K.. Jayapal, "Pre-Silicon Prototyping of a Unified Hardware Architecture for Cryptographic Manipulation Detection Codes", Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on: IEEE, pp. 323-326, 2004.