Reduced complexity architecture for convolution based discrete cosine transform

TitleReduced complexity architecture for convolution based discrete cosine transform
Publication TypeConference Proceedings
Year of Conference2013
AuthorsMamatha, I., RJ. Nikhita, S.. Tripathi, and TSB. Sudarshan
Conference NameInternational Symposium on Electronic System Design (ISED)
Pagination67-71
PublisherIEEE
ISBN Number0769551432
KeywordsDept. of Electronics and communication Engineering.
Abstract

Discrete Cosine Transform is a popular transform used in signal/image processing applications. Reduction in complexity of hardware architecture for the computation of DCT using the convolution based algorithm is proposed. An N point DCT can be computed through 2 pair of [(M-1)/2] point cyclic convolutions where M is an odd number such that N=2M. The proposed architecture uses only a pair of systolic array where inputs are pipelined against the one in literature where 2 pairs of systolic arrays are used. One of the systolic arrays uses processing element with tag bit and the other one does not need a tag bit. The architecture uses 50% less number of processing elements with just an additional increase in computation time by one unit. The architecture is divided into three stages as preprocessor stage, compute stage where a systolic array computes the cyclic convolution and a post processing stage to process the output of the systolic array to get the actual DCT output. It is observed that the proposed architecture has a reduction of about 42%adders and 64% multipliers as compared to the one in literature. Further, the architecture is simulated in ModelSim 6.5 and synthesized using Xilinx ISE10.1using Vertex 5 FPGA as the target device. The simulation results are matched favourably with that of the output obtained by MATLAB R2010a with MSE of1.3861x10-4.