# Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product

Title | Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product |

Publication Type | Book Chapter |

Year of Publication | 2014 |

Authors | Mamatha I, Tripathi S., Sudarshan TSB, Bhattar N |

Book Title | Advances in Signal Processing and Intelligent Recognition Systems |

Pagination | 311-322 |

Publisher | Springer, Cham |

Keywords | Dept. of Electronics and communication Engineering. |

Abstract | A generic 2D systolic array for N point Discrete Fourier Transform using triple matrix product algorithm is proposed. The array can be used for a non power of two sized N point DFT where N=N1N2 is a composite number. It uses an array of size N2×(N1+1) which requires(2N+4N2) multipliers. For a DFT of size 4N2 (i.e multiple of four), an optimized design which requires 4N2number of multipliers is proposed. It is observed that the proposed optimized structure reduces the number of multipliers by 66.6% as compared to the generic array structure while maintaining the same time complexity. Two examples are illustrated, one with non power of two size DFT and another with a DFT of size 4N2. Both the generic and optimized structures use the triple matrix product representation of DFT. The two structures are synthesized using Xilinx ISE 11.1 using the target device as xc5vtx240t-2ff1759 Virtex-5 FPGA. The proposed structure produces unscrambled stream of DFT sequence at output avoiding a necessity of reordering buffer. The array can be used for matrix -matrix multiplication and to compute the diagonal elements of a triple-matrix multiplication. |