Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product

TitleSystolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product
Publication TypeConference Proceedings
Year of Conference2014
AuthorsMamatha, I.., TSB.. Sudarshan, S.. Tripathi, and N.. Bhattar
Conference NameAdvances in Signal Processing and Intelligent Recognition Systems
Pagination311-322
PublisherSpringer, Cham
KeywordsDepartment of Computer Science and Engineering
URLhttps://link.springer.com/chapter/10.1007/978-3-319-04960-1_28